Static Random Access Memory (SRAM) retains information by maintaining a differential charge across a pair of bit lines for each memory cell. One prior art SRAM structure is shown in FIG. 1. FIG. 1 shows a structure 100 of 6 transistor (6T) memory cells 200, each cell of which is shown in greater detail in FIG. 2. The 6T cell 200 includes a word line 202 and a pair of bit lines 204, 206. The word line 202 controls pass gates 208, 210 to allow discharging of the bit lines. The memory cell 200 is programmed or written to by applying a differential voltage across its bit lines, and is read by detecting a differential discharge across the bit lines. Each memory cell 200 includes a storage cell made up of four transistors: PMOS load transistors 212 and cross-coupled NMOS storage transistors 214. The cell is operable in any one of three modes: static mode, write mode, and read mode.
During static mode, charge is maintained on the bit cells by keeping the word line 202 at logic zero (Ground) while precharging the bit lines 204, 206 to VDD.
In write mode, a logic 1 or 0 is programmed into the memory cell 200 by driving the word line 202 to a logic 1 and applying a differential voltage across the bit lines 204, 206 (logic 1 on bit line 204, and logic 0 on bit line 206 programs the cell 200 to a logic 1, and vice versa).
During read mode, a differential voltage is detected across the bit lines by driving the word line 202 to logic 1 and allowing the bit lines to discharge. The logic state of the bit cell 200 determines the nature of the discharge. For instance, if the cell was programmed to logic 0 (bit line 206 driven to logic 1 and bit line 204 driven to logic 0) then bit line 204 would discharge and bit line 206 would remain at VDD since before each read and write, all bitlines are precharged to VDD. Thus, if the logic state of the bit cell is 1, bit line 204 will be maintained at VDD.
Referring to FIG. 1, during static mode all memory cells are precharged to logic 1 by PMOS transistors 102. By applying a low voltage to the gates of the PMOS transistors 102 by means of PRCHG input 104, VDD is applied to the bit lines of the various cells in the structure. During this mode, the word lines are kept low to avoid discharging of the bit lines. During a read or write mode, the precharge PMOS transistors 102 are switched off and one of the word lines is driven to logic 1. This results in all memory cells in that row to start discharging their bit lines, which results in a large active power AC power dissipation. In order to write to or read from a particular memory cell, one of the switches 110 in the multiplexer block 112 is selected. This selects one of the columns. Writing to a memory cell (also referred to as a bit cell) requires the use of a write circuit 114 to apply a differential voltage across the bit lines by providing a differential voltage across the lines 120, 122. During read mode the differential voltage across the bit lines is detected using a sense amplifier and routing this to the output circuit. In FIG. 1, the write circuit and sense amplifier are depicted as a single block 114.
It will be appreciated that during each read or write operation, an entire row of precharged memory cells is discharged, thereby consuming a lot of AC power. It is therefore desirable to reduce this power consumption. One such approach was described in prior US patent application owned by the same assignee and entitled “Low Power SRAM Architecture”. This solution made use of 8 transistor (8T) memory cells 300 as shown in FIG. 3, in which two extra pass gates 302 were provided and controlled by an additional control line 310. As shown in the memory structure of FIG. 4, each of the control lines 310 controls a column of memory cells 300, while the word lines still control rows of memory cells. Thus the control lines 310, in conjunction with the word lines 312, allow a single memory cell 300 to be selected during the read or write operation and thereby cause only a single memory cell to discharge.
While this results in a substantial power saving, each of the additional control lines 310 connects to each of the memory cells in a column. Thus the larger the number of rows in the memory array, the larger the number of memory cells in a column. This presents a substantial load to the control lines 310. Since the control lines 310 have to be charged and discharged whenever there is an address change, a substantial amount of power is consumed by the added control lines. The present invention seeks to address this issue.